(19) Federal Republic of Germany (10) DE 198 12 069 B4 July 07, 2005

Description

[0001] The invention relates to a power amplifier. The invention can be employed in all types of power amplifiers. In particular, it is intended for application in medical devices, in particular in nuclear magnetic resonance imaging apparatuses. In the latter case the power amplifier may be used as a gradient amplifier in order to supply a gradient coil with current.

[0002] When a nuclear magnetic resonance imaging apparatus or a magnetic resonance system is running, magnetic field gradients are produced by the gradient coils. Current flows through each gradient coil; and in an exactly defined current waveform, this current may reach values of up to and including, for example, 300 A or more. The current waveform often exhibits sharp slopes. In order to achieve the requisite high rate of change in the current, it may be necessary to apply a voltage of, for example, 2,000 V or more to the gradient coil.

[0003] Today's gradient amplifiers typically exhibit switching regulators, the output stage transistors of which are operated directly with the demanded voltages and switching frequencies. However, with today's technologies this is possible only for voltages of up to approximately 800 V and for switching frequencies of up to approximately 25 kHz and also necessitates even within these limits a high cost and space requirement. Semiconductors, which can connect more than 800 V at the occurring current intensities with the requisite steepness, are currently not available.

Background Art

[0004] It has already been proposed in the DE 43 04 517 A1 to connect in series at least two controllable voltage sources at the output side in the case of a power supply for predominantly inductive loads. Two control units are designed as the modulators for generating pulse width modulated drive signals for the voltage sources. The switch-on times of the voltage adjustment units, disposed in the voltage sources, are determined by the control units through a comparison of a common triangular signal with a regulator output signal.

[0005] One of the design alternatives, mentioned in the DE 43 04 517 A1, proposes a plurality of voltage sources, which contribute to delivering a peak output voltage. In this case the voltage sources may be driven so as to be offset with respect to time, in order to decrease the ripple of the total output voltage. However, this teaching does not affect a time offset drive of all of the base and peak load voltage sources contributing to the output voltage.

[0006] The DE 40 17 207 A1 discloses a device for feeding a bipolar load. In the case of this device a plurality of direct current buck regulators are driven according to the principle of pulse width modulation. Hence, the uniformly long cycle periods are offset by 1/n of the cycle duration. Each of the buck regulators exhibits a single switching element, in order to connect a direct current of a fixed polarity. The buck regulators are connected in series at the output side and are connected to a bipolar load, for example, a plasma magnetron. The application in gradient amplifiers is not disclosed.

[0007] The problem of filtering the output voltage continues to exist, in particular, in the critical application in medical diagnostic imaging procedures. In this case, a variety of criteria must be taken into consideration. Above all it is desirable that the effective switching frequency of the output voltage be as high as possible, in order to achieve a large distance from the frequency range of the useful current.

[0008] The WO 95/10881 discloses a switching amplifier, wherein a plurality of output stages are also connected in series in the form of controllable voltage sources. Thus, the output stage switching clocks are offset from each other in such a manner that the effective switching frequency of the output voltage is raised. However, even with this feature it is difficult to filter the current waveform in such a way that all faults are suppressed. This requirement raises difficulties, in particular, with respect to image defects, in situations, where power amplifiers are used as gradient amplifiers in a nuclear magnetic resonance imaging apparatus.

Technical Problem

[0009] Against this background, the invention is based on the problem of providing a power amplifier and a method for generating control signals for a power amplifier, the output voltage of which has good properties with respect to filtering the switching clock signals or the switching edges or the parasitic voltages and currents, so that malfunctions of other modules may be avoided.

[0010] The invention solves this problem with a device that exhibits the features disclosed in claim 1 and with a method that exhibits the features disclosed in claim 8. The dependent claims relate to preferred embodiments of the invention.

[0011] The invention proceeds from the basic idea that in a power amplifier conforming with its genre, all of the output stages are driven with switching signals, which are offset from each other. Thus, a common mode charging current, resulting from the coupling capacitances, exhibits alternating positive and negative pulses. Owing to this measure the fundamental frequency of the common mode charging current replicates so that this common mode charging current can be simply filtered out of the entire current flux to the load.

[0012] The invention makes it possible for the first time to produce cost-effectively and with negligible disturbing effects power amplifiers having high switching frequencies (50 kHz or higher) and high output voltages (several kV). The individual output stages, the interconnection of which forms the inventive amplifier, do not have to satisfy any especially high demands and are, therefore, disproportionately more cost effective than a single high power output stage. For example, the advantages of low cost, but relatively slowly switching power transistors (for example, IGBTs - insulated gate bipolar transistors) may be exploited. Moreover, owing to the low switching frequency of the individual output stages, the losses are significantly less.

[0013] In comparison with a power amplifier with a single high power output stage, the invention has, furthermore, the advantage that the steep edged voltage jumps, which occur at each switching clock on the leads to the load (for example, of a gradient coil), only make up a fraction of the total voltage. Thus, it is also easier to filter these voltage swings; and electromagnetic interferences in the high frequency range that could affect the image are suppressed.

[0014] Another advantage of the invention is that the enhanced effective switching frequency of the output voltage also leads to a faster response of the power amplifier to an input voltage, which is to be amplified, and thus to a shorter delay in the feedback control loop.

[0015] Even the common mode charging current, which causes problems in the prior art configurations, can be easily filtered out with the solution, according to the invention.

[0016] The preferred embodiments provide an odd number of output stages. The number of output stages can amount, in particular, to five. The phase angle of the output stage switching clock signals amounts preferably to 360 deg. /n or 180 deg. /n, where n is the number of output stages. In the event of an odd number of output stages, a phase angle of 360 deg. /n is particularly preferred.

[0017] Preferably the total load is distributed uniformly among the individual output stages. The output stages may contribute especially in equal parts and/or in a symmetrical manner to the output voltage. For example, the output stages may be driven in such a manner that they deliver voltage pulses of identical width. In situations, where the input voltage only changes very slowly, the drive pulses of the output stages may be in essence identical, save for the desired time offset. In this case it is guaranteed that in both remagnetizing an inductive load and demagnetizing, the energy is drawn symmetrically from all of the output stage power supply units or fed back into them. Then there is no need for any measures to balance the energy between the power supply units; and the power amplifier acts as a perfect four quadrant adjustment unit. If the input voltage changes quickly, it may occur that for a short period of time (within one switching clock cycle) the output stages exhibit different loads. However, these differences are irrelevant, because they are distributed on average uniformly among the output stages.

[0018] In preferred drive procedures for the power bridge circuits, two output stage voltage pulses, each of these being separated by an output stage free- running mode, are generated in every cycle of the output stage switching clock. The two voltage pulses may correspond to a respective diagonal mode of the bridge circuit; and the two free-running modes can each correspond to a condition of the bridge circuit, wherein a load current can flow unimpeded through the bridge.

[0019] The inventive method is also improved preferably according to the above described or corresponding features.

[0020] Especially in the case of the above described preferred further developments of the invention, there may be, besides the output stages and the load, still other modules of the power amplifier in the load circuit - for example, boosters, resonance circuits, linear output stages or switchable voltage sources. Therefore, the feature that the output voltage is produced as the sum of the output stage voltages, is not regarded as an essential feature of the invention, in particular with respect of the further developments of the drive methods.

Embodiments

[0021] At this point several embodiments of the invention are explained in detail below with reference to the schematic drawings.

[0022] Figure 1 is a schematic circuit diagram of an inventive power amplifier, as already known in principle.

[0023] Figure 2a to Figure 2e depict the voltage waveforms in situations, where the power amplifier is being operated at different degrees of modulation.

[0024] Figure 3 is a schematic circuit diagram of a power amplifier with five output stages.

[0025] Figure 4a and Figure 4b depict the voltage and current waveforms in situations, where the power amplifier in Figure 3 is being operated with different drive methods.

[0026] Figure 5 is a schematic circuit diagram of a power amplifier with four output stages, and

[0027] Figure 6a to Figure 6c depict the voltage and current waveforms in situations, where the power amplifier in Figure 5 is being operated with different drive methods.

[0028] The power amplifier, depicted in Figure 1, is designed as a gradient amplifier of a nuclear magnetic resonance imaging apparatus. It exhibits a plurality of output stages 10.1, 10.2, ..., 10.n, which are connected in series at the output side and are connected to a load 12, which is designed as the gradient coil. The output stages 10.1, 10.2, ..., 10.n generate output stage voltages U_E1, U_E2, ..., U_En, the sum of which is the output voltage U_A of the power amplifier, said output voltage being applied to the load 12. Therefore, U_A = U_E1 + U_E2 + ... + U_En holds true. In situations, where a maximum output voltage U_A of approximately 2,000 V and a logical output stage voltage of a few hundred volts are to be targeted, the number n of output stages 10.1, 10.2, ..., 10.n typically amounts to four, five or six. In the embodiment that is described in this case, n = 5. Alternative designs provide different values.

[0029] Each of the output stages 10.1, 10.2, ..., 10.n exhibits in a way that is known in the art a power bridge circuit 14.1, 14.2, ..., 14.n, which is supplied with a floating intermediate circuit voltage by a respective power supply unit 16.1, 16.2, ..., 16.n. Furthermore, there is a respective buffer capacitor 18.1, 18.2, ..., 18.n for smoothing the intermediate circuit voltages.

[0030] The power bridge circuit 14.1 of the output stage 10.1 exhibits four switching elements 20.1, 22.1, 24.1, 26.1, which may be designed, for example, as IGBTs with integrated free-wheeling diodes. The respective pairs of switching elements 20.1, 22.1 and 24.1, 26.1 are connected in series, in order to form a respective bridge arm between the two poles of the intermediate circuit voltage. The output stage voltage U_E1 is tapped at the bridge cross arm. One driver 28.1, 30.1, 32.1, 34.1 is assigned to each of the switching elements 20.1, 22.1, 24.1, 26.1. The drivers 28.1, 30.1, 32.1, 34.1 are driven by a control circuit, which is common to all of the output stages 10.1, 10.2, ..., 10.n and which makes available the pulse width modulated control signals to all of the switching elements. The control circuit may be constructed as either a uniform module or of a plurality of modules, of which one module is assigned to each output stage 10.1, 10.2, ..., 10.n.

[0031] The other output stages 10.2, ..., 10.n are constructed in a manner analogous to the output stage 10.1 with the switching elements 20.2, 22.2, 24.2, 26.2; ...; 20.n; 22.n, 24.n, 26.n and the drivers 28.2, 30.2, 32.2, 34.2; ...; 28.n, 30.n, 32.n, 34.n.

[0032] When the power amplifier is operating, the power bridge circuits 14.1, 14.2, ..., 14.n are driven according to the pulse width modulation process, which is known in the art. To this end, it is possible, in principle, to use a plethora of different methods. However, the preferred method is the modulation method, which is described in detail in the DE 34 38 034 A1 and the DE 40 24 160 A1. However, an especially preferred method is described in even greater detail below. With respect to the modulation methods, the disclosure of the cited documents is incorporated explicitly in the present application.

[0033] The important factor is that the switching clocks, underlying the pulse width modulation, are offset from each other in a way that results in a replication of the effective switching clock frequency of the output voltage U_A as compared to the switching clocks of the individual output stage voltages U_E1, U_E2, ..., U_En. Moreover, this division makes it possible to prevent large voltage jumps in the output voltage U_A. These effects are illustrated in the examples, depicted in Figure 2a to Figure 2e, for the case of a power amplifier, exhibiting five output stages 10.1, 10.2, ..., 10.5.

[0034] In the case of the modulation method, on which Figure 2a to Figure 2e are based, each output stage 10.1, 10.2, ..., 10.5 produces two voltage pulses in every switching clock. Said voltage pulses exhibit a phase angle of 180 deg. in relation to each other; and each of these voltage pulses is separated by a free-running mode. During the free-running mode, the output stage 10.1, 10.2, ..., 10.5 is in a state that is conductive for the current flux in the load circuit. The free-running mode is depicted in Figure 2a to Figure 2e by a low level of the output stage voltages U_E1, U_E2, ..., U_En. The switching clocks of the output stages 10.1, 10.2, ..., 10.5 are offset from each other by 180 deg. /5 = 36 deg. However, this special offset is shown here solely for the purpose of explaining the superpositioning of the output voltages of the individual output stages and is not covered by the present invention. The switching frequency of each output stage 10.1, 10.2, ..., 10.5 amounts to 10 kHz; and the switching frequency of the output voltage U_A always amounts to 50 kHz. Apart from the time offset and the changes in the pulse width, said changes being induced by an input voltage level of the power amplifier that changes during the time offset, each output stage 10.1, 10.2, ..., 10.5 is driven with identical switching signals. Therefore, each output stage 10.1, 10.2, ..., 10.5 produces voltage pulses having essentially the same width; and in all operating states the total load is divided uniformly among all output stages 10.1, 10.2, ..., 10.5, so that there would be no need for expensive energy balancing measures.

[0035] Figure 2a shows the waveforms of the output stage voltages U_E1, U_E2, ..., U_E5 in situations, where the modulation of the power amplifier is low. The relatively short voltages pulses, generated by the output stages 10.1, 10.2, ..., 10.5, alternate in the output voltage U_A without overlapping. Therefore, the sum is the product of the desired quintupling of the frequency at an output voltage U_A, which is equivalent at a maximum to the amount of one output stage voltage U_E1, U_E2, ..., U_E5.

[0036] Figure 2b depicts a somewhat larger modulation of the power amplifier. In this case the voltage pulses of an output stage 10.1, 10.2, ..., 10.5 overlap those of the output stage 10.1, 10.2, ..., 10.5, which follows in the switching clock sequence. At this point the output voltage U_A amounts at a maximum to twice the output stage voltage U_E1, U_E2, ..., U_E5. The high switching clock frequency in the output voltage U_A is maintained. In this case, too, the output voltage U_A varies only by the amount of a maximum output stage voltage U_E1, U_E2, ..., U_E5.

[0037] Figure 2c and Figure 2d show even higher modulation levels of the power amplifier. In Figure 2c the width of the output stage voltage pulses ranges from 2/5 x 180 deg. to 3/5 x 180 deg.; and in Figure 2d from 3/5 x 180 deg. to 4/5 deg. x 180 deg. The mean output voltage U_A is a corresponding fraction of the maximally attainable quintuple output stage voltage.

[0038] In Figure 2e the potential full modulation of the power amplifier is almost reached. The high switching frequency and the relatively small voltage jumps of the output voltage U_A continue to exist.

[0039] The properties of one modulation method are described in more detail below. In this modulation method every cycle of the output stage switching clock is divided into four sections. In these sections the output stage assumes four operating states, and in particular two free-running operating states (an upper and lower free‑running mode) and two diagonal operating states. These four operating states are explained below by means of the example of the output stage 10.1, shown in Figure 1.

[0040] In the upper free-running mode, the switching elements 20.1 and 24.1 are conducting (either by active drive or owing to the integrated free-wheeling diodes). Thus, the current path going through the output stage 10.1 is coupled with the positive pole of the power supply unit 16.1. Correspondingly in the lower free-running mode the switching elements 22.1 and 26.1 are conducting, so that the current path through the output stage 10.1 is connected to the minus pole of the power supply unit 16.1. The first diagonal mode results from the transition from the upper to the lower free-running mode and is, therefore, referred to the "falling diagonal mode". In this case either the switching elements 20.1 and 26.1 or the switching elements 22.1 and 24.1 are conducting as a function of the desired change in the current in the load circuit. The same applies to the second diagonal mode, which results from the transition from the lower to the upper free-running mode and is, therefore, referred to as the "rising diagonal mode". The rate of current change in the load circuit is determined by the duration of the rising and falling diagonal mode. In each diagonal mode - thus, twice per switching clock cycle -, the output stage 10.1 produces a voltage pulse of the output stage voltage U_E1. The same applies to the other output stages 10.2, ..., 10.n of the power amplifier.

[0041] In alternative design variants of this method other switching elements may be driven, in addition to the aforementioned switching elements, in the individual operating states of an output stage. In particularly preferred embodiments the modulation of the output stages is carried out in accordance with the aforementioned DE 40 24 160 A1. In this case, two switching elements, lying diagonally opposite each other in the power bridge circuit, are periodically clocked in every direction of the load current; and, in addition, two switching elements, which lie in series in the bridge circuit, are clocked in anti-phase. Owing to this drive method, good results are produced during a change in current direction in the load circuit and with very narrow pulse widths.

[0042] Figure 3 is once more a schematic drawing of the power amplifier, which is connected to the load 12 and which exhibits five output stages 10.1, 10.2, ..., 10.5, which are constructed in the same way as in Figure 1. Furthermore, Figure 3 depicts the capacitances 36.1, 36.2, ..., 36.5, in order to illustrate the coupling capacitances between each output stage 10.1, 10.2, ..., 10.5, on the one hand, and the ground or respectively earth and/or the other components of the imaging apparatus. Furthermore, the (significantly larger) coupling capacitance of the load 12, designed as the gradient coil, is indicated by means of one capacitance 38.

[0043] Figure 4a shows the power amplifier from Figure 3 in the same operating state and with the same drive method as in Figure 2a, thus with less modulation and an offset of the output stage switching clocks of 180 deg. /5 = 36 deg. In this case, too, it must be pointed out that this type of offset is not covered by the invention, but rather serves only to explain the technical problem. The five curves S_E1, S_E2, ..., S_E5 represent the voltage potentials at the output terminals of each output stage 10.1, 10.2, ..., 10.5.

[0044] Therefore, the output stage 10.1 (voltage potential curve S_E1) is, first of all, in the upper free-running mode. The switching elements 20.1 and 24.1 are conducting, so that both output terminals of the output stage 10.1 are connected to the plus pole of the output stage power supply unit 16.1 and exhibit a high voltage potential. In the phase angle range around 0 deg., one side of the bridge changes to a minus potential, whereas the other side continues to be at the high potential. This falling diagonal mode is shown by the double contour of the voltage potential curve S_E1. The lower free-running mode follows; in this mode the switching elements 22.1 and 26.1 are conducting; and, hence, both output terminals exhibit the potential of the negative intermediate circuit voltage. In the range around 180 deg., the two sides of the bridge alternately change over in succession to the high potential. The time offset between the "reversal" of the two bridge sides matches the duration of the rising diagonal mode. After the two bridge sides have reversed, the upper free-running mode is reached again.

[0045] The output voltage curve U_A in Figure 4a is identical to the one shown in Figure 2a. The bottom-most curve in Figure 4a indicates the common mode charging current I_GTL, which flows, owing to the coupling capacitances 36.1, 36.2, ..., 36.5 and 38 at each potential change, through the lines running between the power amplifier and the load 12. The negative potential change of a falling diagonal mode induces a negative pulse of the common mode charging current; and inversely a rising diagonal mode produces a positive current pulse. The common mode charging current I_GTL superposes the useful current and can lead to noises that affect the image. Therefore, it is desirable to select the drive method in such a manner that the common mode charging current is minimized or at least exhibits a current waveform that can be easily filtered.

[0046] In the drive method with a switching clock offset of 36 deg., as shown in Figure 4a, the blocks, each exhibiting five falling and rising diagonal modes, alternate in succession. Correspondingly the common mode charging current I_GTL exhibits in succession five pulses of the same polarity. Hence, the common mode charging current I_GTL contains, as the fundamental mode, the switching frequency of the output stages 10.1, 10.2, ..., 10.5. This method renders an effective filtering more difficult.

[0047] Figure 4b shows an alternative drive method in accordance with one embodiment of the invention. According to this method, the switching clock offset is 360 deg., divided by the number of output stages. In the present case they are 360 deg. /5 = 72 deg. This offset of the output stage switching signals also has the effect of increasing the effective switching frequency of the output voltage U_E and of reducing the voltage jumps in the output voltage U_E by a factor of five. Moreover, the common mode charging current I_GTL between the load 12 and the power amplifier exhibits alternating positive or negative pulses. Hence, the base frequency of the common mode charging current I_GTL is five times the switching frequency of an output stage 10.1, 10.2, ..., 10.5. As a result, this current can be easily and largely filtered out of the entire current flux from and to the load 12. With this drive method it is possible to improve the filterability of the load current with respect to the prior art arrangements.

[0048] Figure 5 shows a power amplifier that is similar to the one shown in Figure 3. In this case, however, four output stages 10.1, 10.2, 10.3, 10.4 are provided.

[0049] Figure 6a shows the properties of the amplifier from Figure 5 for a drive method, analogous to the one in Figure 4a. In this case the switching clocks of the output stages 10.1, 10.2, 10.3, 10.4 are offset from each other by 180 deg. /4 = 45 deg. This type of offset is not covered by the invention, but rather serves only to illustrate the technical problem. Hence, the results are the advantages, described in connection with Figure 4a, - that is, an increase in the effective switching frequency and a decrease in the voltage jumps in the output voltage U_A. However, there is the drawback of a poor filterability of the common mode charging current I_GTL. In Figure 6b, the offset of the output stage switching clocks is 90 deg., thus 360 deg., divided by the number of output stages 10.1, 10.2, 10.3, 10.4. This type of offset is also not covered by the invention, but rather serves only to explain the technical problem. Precisely in this case the common mode interferences are eliminated, since two bridges always switch simultaneously in the opposite direction. However, the effective clock frequency of the output voltage U_A is not quadrupled, but rather only doubled. Even the voltage jumps of the output voltage U_A are relatively high - that is, equal to twice the operating voltage of an output stage 10.1, 10.2, 10.3, 10.4. The two latter properties make it difficult to filter the output voltage U_A.

[0050] Finally Figure 6c shows, as an additional embodiment of the invention, a drive method, in which the offset between the output stage switching clocks amounts to 45 deg., just as in Figure 6a. However, at the same time the power bridge circuits 14.2 and 14.4 of the second and fourth output stages 10.2 and 10.4 are driven so as to be inverted. In contrast to the drawing in Figure 5, the output terminals of these two output stages 10.2 and 10.4 are exchanged, in order to achieve an unchanged output voltage U_A. In this drive method the output voltage U_A exhibits optimal values with respect to the switching frequency and the voltage swings. The pulses of the common mode charging current I_GTL alternate in their direction within a half cycle (phase angle 180 deg.). After every half cycle, however, there is, nevertheless, a phase jump of 45 deg. This phase jump in turn makes it difficult to filter these disturbing currents.

[0051] The above described different parameters of the drive method (number of output stages, offset, inversion of the individual signals, ...) may be combined in a number of different ways in other design alternatives, in order to achieve yet other variants. Currently the inventors deem a power amplifier with an odd number of output stages, in particular five output stages, and one offset of 360 deg., divided by the number of output stages, to be the best way to carry out the invention.

Patent Claims

1. Power amplifier, in particular a gradient amplifier of a nuclear magnetic resonance imaging apparatus, with the following features:

- at least two output stages (10.1, 10.2, ..., 10.n), each of which exhibits one power bridge circuit (14.1, 14.2, ..., 14.n), are connected in series at the output side, in order to generate a respective output stage voltage (U_E1, U_E2, ..., U_En) by pulse width modulation according to a respective output stage switching clock,

- an output voltage (U_A) of the power amplifier is generated as the sum of the output stage voltages (U_E1, U_E2, ..., U_En),

- the output stage switching clocks of the output stages (10.1, 10.2, ..., 10.n) are offset relative to each other, in order to increase the effective switching frequency of the output voltage (U_A),

- the coupling capacitances (36.1, 36.2, ..., 36.5 and 38) of the output stages (10.1, 10.2, ..., 10.n) and a load (12) at each potential change cause the common mode charging current (I_GTL) to flow through lines, running between the power amplifier and the load (12),

- the common mode charging current (I_GTL) exhibits alternating positive and negative pulses.

2. Power amplifier, as claimed in claim 1, characterized in that the number (n) of output stages (10.1, 10.2, ..., 10.n) is odd and that the output stage switching clocks are offset from each other by a phase angle of 360 deg., divided by the number (n) of output stages (10.1, 10.2, ..., 10.n).

3. Power amplifier, as claimed in claim 2, characterized in that the number (n) of output stages (10.1, 10.2, ..., 10.n) is five.

4. Power amplifier, as claimed in claim 1, characterized in that the number of output stages (10.1, 10.2, ..., 10.n) is even and that the output stage switching clocks are offset from each other by a phase angle of 180 deg., divided by the number (n) of output stages (10.1, 10.2, ..., 10.n).

5. Power amplifier, as claimed in any one of the claims 1 to 4, characterized in that the output stages (10.1, 10.2, ..., 10.n) contribute in equal parts and/or in a symmetrical manner to the output voltage (U_A).

6. Power amplifier, as claimed in any one of the claims 1 to 5, characterized in that each output stage (10.1, 10.2, ..., 10.n) generates two output stage voltage pulses, each of these being separated by an output stage free-running mode, in every cycle of the output stage switching clock.

7. Power amplifier, as claimed in any one of the claims 1 to 5, characterized in that at each output stage (10.1, 10.2, ..., 10.n) a first diagonal mode, a lower free-running mode, a second diagonal mode and an upper free-running mode take place in every cycle of the output stage switching clock.

8. Method for generating control signals for a power amplifier, in particular a gradient amplifier of a nuclear magnetic resonance imaging apparatus, with the following features:

- power bridge circuits (14.1, 14.2, ..., 14.n) are driven by at least two output stages (10.1, 10.2, ..., 10.n), which are connected in series at the output side, by pulse width modulation according to a respective output stage switching clock, in order to generate a respective output stage voltage (U_E1, U_E2, ..., U_En),

- an output voltage (U_A) of the power amplifier is generated as the sum of the output stage voltages (U_E1, U_E2, ..., U_En),

- the output stage switching clocks of the output stages (10.1, 10.2, ..., 10.n) are offset relative to each other, in order to increase the effective switching frequency of the output voltage (U_A),

- the common mode charging current (I_GTL) exhibits alternating positive and negative pulses.

9. Method, as claimed in claim 8, characterized in that the number (n) of output stages (10.1, 10.2, ..., 10.n) is odd and that the output stage switching clocks are offset from each other by a phase angle of 360 deg., divided by the number (n) of output stages (10.1, 10.2, ..., 10.n).

10. Method, as claimed in claim 9, wherein the number of output stages is five.

11. Method for generating control signals, as claimed in claim 8, characterized in that the number of output stages (10.1, 10.2, ..., 10.n) is even and that the output stage switching clocks are offset from each other by a phase angle of 180 deg., divided by the number (n) of output stages (10.1, 10.2, ..., 10.n).

12. Method, as claimed in any one of the claims 8 to 11, characterized in that the output stages (10.1, 10.2, ..., 10.n) contribute in equal parts and/or in a symmetrical manner to the output voltage (U_A).

13. Method, as claimed in any one of the claims 8 to 12, characterized in that each output stage (10.1, 10.2, ..., 10.n) generates two output stage voltage pulses, each of these being separated by an output stage free-running mode, in every cycle of the output stage switching clock.

14. Method, as claimed in any one of the claims 8 to 13, characterized in that each output stage (10.1, 10.2, ..., 10.n) carries out a first diagonal mode, a lower free-running mode, a second diagonal mode and an upper free-running mode in every cycle of the output stage switching clock.

7 sheets of drawings follow.

key to figures

Attached Drawings

Figure 1

(State of the Art)